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Si5 54
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Units
Supply Voltage 1
V DD
3.3 V option
2.5 V option
1.8 V option
2.97
2.25
1.71
3.3
2.5
1.8
3.63
2.75
1.89
V
V
V
Supply Current
Output enabled
LVPECL
—
120
130
I DD
CML
LVDS
CMOS
Tristate mode
—
—
—
—
108
99
90
60
117
108
98
75
mA
mA
Output Enable (OE)
and Frequency Select FS[1:0] 2
Operating Temperature Range
T A
V IH
V IL
0.75 x V DD
—
–40
—
—
—
—
0.5
85
V
V
oC
Notes:
1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 10 for further details.
2. OE and FS[1:0] pins include a 17 k ? resistor to VDD.
Table 2. V C Control Voltage Input
Parameter
Control Voltage Tuning Slope
1,2,3
Symbol
Test Condition
10 to 90% of V DD
Min
—
Typ
33
Max
—
Units
ppm/V
45
K V
90
135
180
356
Control Voltage Linearity 4
Modulation Bandwidth
V C Input Impedance
Nominal Control Voltage
Control Voltage Tuning Range
L VC
BW
Z VC
V CNOM
V C
BSL
Incremental
@ f O
–5
–10
9.3
500
—
0
±1
±5
10.0
—
V DD /2
+5
+10
10.7
—
—
V DD
%
%
kHz
k ?
V
V
Notes:
1. Positive slope; selectable option by part number. See Section 3. "Ordering Information" on page 10.
2. For best jitter and phase noise performance, always choose the smallest K V that meets the application’s minimum APR
requirements. See “AN266: VCXO Tuning Slope (K V ), Stability, and Absolute Pull Range (APR)” for more information.
3. K V variation is ±10% of typical values.
4. BSL determined from deviation from best straight line fit with V C ranging from 10 to 90% of V DD . Incremental slope
determined with V C ranging from 10 to 90% of V DD .
2
Rev. 1.1
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